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1 datasheet 5a single channel high efficiency dc/dc step-down power module ISL8205M the ISL8205M power module is a single channel synchronous step-down complete power supply, capable of delivering up to 5a of continuous current. operat ing from a single 2.6v to 5.5v input power rail and integrating controller, power inductor and mosfets, the ISL8205M only requires a few external components to operate and is optimized for space constrained and portable battery operated applications. based on current mode pwm control scheme, the ISL8205M provides a fast transient respon se and excellent loop stability as well as a very low duty cycl e with an adjustable output voltage as low as 0.6v and better than 1.6% accuracy over line and load conditions. operation fr equency is selectable through an external resistor, with a 1. 8mhz default setting, or may be synchronized with an external clock signal up to 3.5mhz. the ISL8205M also implements a selectable pfm mode to improve light-load efficiency and a 100% duty cycle ldo mode to extend battery life. a programmable soft-start reduces the inrush current required from the input supply while an automatic output discharge ensures a soft stop. dedicated enable pin and power-good flag allow for easy system power rails sequencing. an array of protection features, including input undervoltage lockout (uvlo), over-temperature, overcurrent/short-circuit with hiccup mode, overvoltag e and negative overcurrent, guarantees safe operations under abnormal operating conditions. the ISL8205M is available in a compact rohs compliant 22 ld 4.5x7.5x1.85mm qfn package. related literature ? tb389 , ?pcb land pattern design and surface mount guidelines for qfn packages? ? ug072 , ?ISL8205Meval1z evaluation board user guide? features ? 5a single channel complete power supply - integrates controller, mosfets and inductor - pin/function compatible with the 3a isl8202m ? 2.6v to 5.5v input voltage range ? adjustable output voltage range - as low as 0.6v with 1.6% accuracy over line/load/temperature -up to 95% efficiency ? default 1.8mhz current mode control operations - 680khz to 3.5mhz resistor adjustable - external synchronization up to 3.5mhz - selectable light-load efficiency mode - 100% duty cycle ldo mode ?programmable soft-start ? soft-stop output discharge ? dedicated enable pi n and power-good flag ? uvlo, over-temperature, overcurrent, overvoltage and negative overcurrent protections - overcurrent/short-circuit hiccup mode ? 4.5mmx7.5mmx1.85mm 22 ld qfn package applications ? dc to dc pol power module ? c/p, fpga and dsp power ? portable equipment ? battery operated equipment figure 1. typical application diagram at 5 vin , 1.2v out , 1.6mhz f sw , 5a figure 2. efficiency vs load 5v in vin en pg sync ss vout fs epad ISL8205M sgnd pgnd sw vsense comp fb 2x22f 2.6v to 5.5v input c in r fs 124k 2x22f c out 1.2v 5a output r set 100k c ff 820pf 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 00.511.522.533.544.55 load current (a) vout=1.2v, fsw=1.6mhz pwm vout=1.2v, fsw=1.6mhz pfm vout=3.3v, fsw=3mhz pfm vout=3.3v, fsw=3mhz pwm efficiency (%) august 15, 2016 fn8755.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL8205M 2 fn8755.3 august 15, 2016 submit document feedback table of contents functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 short-circuit protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pfm (skip) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 negative current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 external synchronization control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 discharge mode (soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 recommended switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 feed-forward capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal consideration and current derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pcb layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ISL8205M 3 fn8755.3 august 15, 2016 submit document feedback functional block diagram figure 3. functional block diagram eamp soft- start bandgap shutdown vref ss en ov uv 0.8v fb 0.85 x vref 1ms delay pg 0.5v comp comp slope comp oscillator pwm/pfm logic controller protection hs driver fs sync shutdown ls driver csa ocp skip negative current sensing shutdown iset threshold vin sw pgnd sgnd pgnd l vout 51 vsense scp zero-crossing sensing sgnd 17 15 19 12 18 16 13 11 21 6 9sw 3 20 14 pgnd pgnd 4 22 vsense 2 fb 1 ?? 100 ?? 100k ?? 0.5%
ISL8205M 4 fn8755.3 august 15, 2016 submit document feedback pin configuration ISL8205M (22 ld qfn) top view pin descriptions pin number pin name description 1, 19 fb voltage setting pin. module output voltage is set by connecting a resistor, r set , from this pin to sgnd. a ceramic capacitor is also recommended to be placed in parallel with r set from fb to sgnd to ensure system stability in extreme operation conditions. refer to table 2 on page 14 for the resistor and capacitor values for various typical output voltage. 2, 4 vsense voltage sense pin. pins 2 and 4 are shorted together internally. an internal 51 resistor is connected from vout (pad 6) to vsense for local output voltage feedback in case remo te sensing is not present. to achieve best regulation performance at point of load, remote sensing tr ace needs to be directly routed to vsense. 3, 14 pgnd power ground. power ground pins. place output capacitor across vout and pgnd close to pin 3 since it is the return path for output current. 5, 7, 8, 10 nc no connection pins. these pins have no connections inside. leave these pins floating. 6vout power output. power output of the module. output capacitors should be placed across this pad and pin 3 pgnd and close to the module. apply load between this pin an d pgnd pin 3. output voltage range: 0.6v to 5v. 9, 21 sw switching node. these pins can be used to monitor switch node wa veform to examine switching frequency. these pins can also be used for snubber connection. to improve system efficiency, it is recommended to connect pins 9 and 21 with wide copper shape. however, avoid connecting sw to large copper shape to minimize radiated emi noise. 11 vin power input. input voltage range: 2.6v to 5.5v. tie directly to the in put rail. it is required to have a minimum total input capacitance of 44f at module input. add additional capacita nce if possible. use x5r or x7 r ceramic capacitors. it is critical to place input ceramic capacitors as close as possible to module input. refer to ? pcb layout recommendations ? on page 19 for more information. 12 pg power-good pin. power-good is an open-drain output. use a 10k to 100k pull-up resistor connected between vin and pg. during power-up or en pin start-up , pg rising edge is delayed by 1ms upon output reached within regulation. 13 sync synchronization pin. mode selection pin. connect to logic high or in put voltage vin for pwm mode. connect to logic low or ground for pfm mode. connect to an external clock for sy nchronization with the positive edge trigger. there is an internal 1m pull-down resistor to prevent an undefined logic state in case sync pin is floating. therefore, pfm mode is enabled when sync is left floating. 15 en power enable pin. enables the output, when driven high. shuts down the output and discharges the output capacitor when driven low. typically tie to vin pin directly. do not leave this pin floating. 1 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 fb fb vsense pgnd vsense nc vout nc nc sw nc vin pg sync pgnd comp ss fs en pgnd sgnd sw 7 . 5 m m 4 . 5 m m 1 . 8 5 m m
ISL8205M 5 fn8755.3 august 15, 2016 submit document feedback 16 fs frequency selection pin. this pin sets the module switching frequency. the default frequency is 1.8mhz if fs is connected to vin. in spite of default setting, a resistor, r fs , can be connected from the fs pin to sgnd to adjust switching frequency ranging from 680khz to 3.5mhz. 17 ss soft-start pin. ss is used to adjust the soft-start time. connect to sgnd for internal 1ms rise time. connect a capacitor from ss to sgnd to adjust the soft-start time. the capacitor value should be less than 33nf to ensure proper operation. 18 comp compensation pin. comp is the output of the voltage feedback erro r amplifier. for most applications, the internal compensation network can be used to stabilize the system and achieve optimal transient response. this can be done by directly connecting comp to vin. for other applications where external compensation is desired, comp needs to be disconnected from vin and tied to the external compensation network. exposed pad 20 pgnd the exposed pad is connected internally to pgnd. solid connection should be made between pad 20 and pgnd plane on pcb. place as many vias as possible under the pad conn ecting to pgnd plane(s) for optimal electrical and thermal performance. refer to ? pcb layout recommendations ? on page 19 for more information. 22 sgnd signal ground pin. connect pcb sgnd plane to this pin. internally, this pin is single-point connected to module pgnd. pin descriptions (continued) pin number pin name description ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) tape and reel (units) package (rohs compliant) pkg. dwg. # ISL8205Mirz-t ISL8205M -40 to +85 4k 22 ld qfn l22.4.5x7.5 ISL8205Mirz-t7a ISL8205M -40 to +85 250 22 ld qfn l22.4.5x7.5 ISL8205Meval1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil plastic packaged products are rohs compliant by eu exemption 7c-i and employ special pb-free material sets, mo lding compounds/die attach materials, and 100% matte tin plate plus anneal (e3) term ination finish which is compatible with both snpb and pb-free s oldering operations. intersil rohs compliant products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free require ments of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for ISL8205M . for more information on msl, please see technical brief tb363 . table 1. key differences between family of parts part number max output current i out (dc) ISL8205M 5a isl8203m 3a dual, 6a single isl8202m 3a
ISL8205M 6 fn8755.3 august 15, 2016 submit document feedback absolute maximum ratings (reference to gnd) thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.8v (dc) or 7v (20ms) en, fs, pg, sync, vfb . . . . . . . . . . . . . . . . . . . . . . . .-0.3v (dc) to vin +0.3v sw . . . . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or 7v (20ms) comp, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd ratings human body model (tested per js-001-2010) . . . . . . . . . . . . . . . . . . 2kv charged device model (tested per js-002-2014) . . . . . . . . . . . . . . 750v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v latch-up (tested per jesd-78d; class 2, level a) . . . . . 100ma at +85c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 22 ld qfn ( notes 4 , 5 ) . . . . . . . . . . . . . . . . 27.4 4.8 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6v to 5.5v v out voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6v to 5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 5a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on the ISL8205Meval1z evaluation board with ?direct attach? features. refer to ISL8205Meval1z user guide for evaluation board details. also see tech brief tb379 for general thermal metric information. 5. for ? jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, typical specifications are measured at v in = 3.6v, v out = 1.2v, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit input supply v in undervoltage lockout threshold ( note 7 )v uvlo rising, no load 2.3 2.5 v falling, no load 2.10 2.25 v quiescent supply current i vin sync = gnd, en = high, i out = 0a 50 a sync = v in , f sw = 1.6mhz, en = high, i out =0a 18 24 ma shutdown supply current i sd sync = gnd, v in = 5.5v, en = low 5 20 a output regulation output continuous current range i out(dc) 5 a line regulation v out/ v out v in = 2.6v to 5.5v, v out = 1.2v, f sw = 1.6mhz, i out = 0a, pwm mode 0.65 % v in = 2.6v to 5.5v, v out = 1.2v, f sw = 1.6mhz, i out = 5a, pwm mode 0.46 % load regulation v in = 5v, v out = 1.2v, f sw = 1.6mhz, i out =0ato5a, pwm mode 0.6 % v in = 5v, v out = 3.3v, f sw = 3mhz, i out =0ato5a, pwm mode 0.62 % output voltage accuracy ( note 8 ) over line/load/temperature range, pwm mode, v out = 1.2v to 3.3v -1.6 1.6 % output ripple voltage v out v in = 5v, 2x22f ceramic output capacitor, pwm mode i out = 0a, v out = 1.2v, f sw = 1.6mhz 11 mv p-p i out = 5a, v out = 1.2v, f sw = 1.6mhz 12 mv p-p i out = 0a, v out = 3.3v, f sw = 3mhz 8 mv p-p i out = 5a, v out = 3.3v, f sw = 3mhz 10 mv p-p reference voltage ( note 7 )v ref 0.594 0.600 0.606 v
ISL8205M 7 fn8755.3 august 15, 2016 submit document feedback vfb bias current ( note 7) i fb v fb = 0.75v 0.1 a soft-start ramp time cycle ( note 7 ) ss = gnd 1 ms soft-start charging current ( note 7 )i ss v ss = 0.1v 1.45 1.85 2.25 a dynamic characteristics voltage change for positive load step v out-dp current slew rate = 1a/s, v in = 5v, 2x22f ceramic output capacitor v out =1.2v, i out = 0a to 5a, f sw = 1.6mhz 120 mv p-p v out =3.3v, i out = 0a to 5a, f sw = 3mhz 69 mv p-p voltage change for negative load step v out-dp current slew rate = 1a/s, v in = 5v, 2x22f ceramic output capacitor v out =1.2v, i out = 5a to 0a, f sw = 1.6mhz 127 mv p-p v out =3.3v, i out = 5a to 0a, f sw = 3mhz 79 mv p-p overcurrent protection ( note 7 ) current limit blanking time t ocon 17 clock pulses overcurrent and auto restart period t ocoff 8 ss cycle positive peak overcurrent limit i plimit 7.5 9.0 11.0 a positive skip limit i skip 1.0 1.3 1.8 a zero cross threshold -300 300 ma negative current limit i nlimit -4.5 -3.0 -1.5 a compensation ( note 7 ) current sensing gain r t 0.119 0.140 0.166 error amplifier transconductance internal compensation 60 a/v external compensation 120 a/v switch node ( note 7 ) p-channel mosfet on-resistance v in = 5v, i o = 200ma 36 63 m v in = 2.7v, i o = 200ma 52 89 m n-channel mosfet on-resistance v in = 5v, i o = 200ma 13 30 m v in = 2.7v, i o = 200ma 17 36 m sw maximum duty cycle 100 % sw minimum on-time sync = high 115 ns oscillator nominal switching frequency f sw sync = v in 1600 1835 2070 khz f sw with r fs = 261k 800 khz f sw with r fs = 124k 1600 khz sync logic low to high transition range 0.70 0.75 0.80 v sync hysteresis 0.15 v sync logic input leakage current v in = 3.6v 3.6 5.0 a electrical specifications unless otherwise noted, typical specifications are measured at v in = 3.6v, v out = 1.2v, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
ISL8205M 8 fn8755.3 august 15, 2016 submit document feedback pg ( note 7 ) output low voltage 0.3 v pg pin leakage current pg = v in 0.01 0.10 a ovp pg rising threshold 0.80 v uvp pg rising threshold 80 85 90 % uvp pg hysteresis 30 mv pgood delay time (rising edge) time from vout reaching regulation 0.5 1.0 2.0 ms pgood delay time (falling edge) 7.5 s en ( note 7 ) logic input low 0.4 v logic input high 0.9 v enable logic input leakage current pulled up to 3.6v 0.1 1.0 a thermal shutdown temperature rising 150 c thermal shutdown hysteresis temperature falling 25 c notes: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. parameters with min and/or max limits are 100% tested for internal ic prior to module assembly, unless otherwise specified. t emperature limits established by characterization and are not production tested. 8. a 0.1% tolerance resistor is used for r set . electrical specifications unless otherwise noted, typical specifications are measured at v in = 3.6v, v out = 1.2v, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
ISL8205M 9 fn8755.3 august 15, 2016 submit document feedback typical performance characteristics efficiency t a = +25c. figure 4. efficiency t a = +25c, v in = 3.3v pfm mode figure 5. efficiency t a = +25c, v in = 5v pfm mode figure 6. efficiency t a = +25c, v in = 3.3v pwm mode figure 7. efficiency t a = +25c, v in = 5v pwm mode output voltage ripple t a = +25c. figure 8. v in = 5v, v out = 3.3v, i out = 0a, f sw = 3mhz, c out = 2x22f ceramic capacitors figure 9. v in = 5v, v out = 3.3v, i out = 5a, f sw = 3mhz, c out = 2x22f ceramic capacitors 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 load current (a) vout=1v, fsw=1.3mhz vout=1.2v, fsw=1.6mhz vout=1.8v, fsw=2mhz vout=2.5v, fsw=2.5mhz efficiency (%) 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 load current (a) vout=1v, fsw=1.3mhz vout=1.2v, fsw=1.6mhz vout=1.8v, fsw=2mhz vout=2.5v, fsw=2.5mhz vout=3.3v, fsw=3mhz efficiency (%) 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 00.511.522.533.544.55 load current (a) vout=1v, fsw=1.3mhz vout=1.2v, fsw=1.6mhz vout=1.8v, fsw=2mhz vout=2.5v, fsw=2.5mhz efficiency (%) 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 00.511.522.533.544.55 load current (a) vout=1v, fsw=1.3mhz vout=1.2v, fsw=1.6mhz vout=1.8v, fsw=2mhz vout=2.5v, fsw=2.5mhz vout=3.3v, fsw=3mhz efficiency (%) 20mv/div 1s/div 20mv/div 1s/div
ISL8205M 10 fn8755.3 august 15, 2016 submit document feedback figure 10. v in = 5v, v out = 1.2v, i out = 0a, f sw = 1.6mhz, c out = 2x22f ceramic capacitors figure 11. v in = 5v, v out = 1.2v, i out = 5a, f sw = 1.6mhz, c out = 2x22f ceramic capacitors figure 12. v in = 3.3v, v out = 2.5v, i out = 0a, f sw = 2.5mhz, c out = 2x22f ceramic capacitors figure 13. v in = 3.3v, v out = 2.5v, i out = 5a, f sw = 2.5mhz, c out = 2x22f ceramic capacitors load transient response t a = +25c, load current step slew rate: 1a/s. figure 14. v in = 5v, v out = 1v, i out = 0 to 5a, f sw = 1.3mhz, c out = 2x22f ceramic capacitors figure 15. v in = 5v, v out = 1.2v, i out = 0 to 5a, f sw = 1.6mhz, c out = 2x22f ceramic capacitors typical performance characteristics (continued) 1s/div 20mv/div 20mv/div 1s/div 20mv/div 1s/div 20mv/div 1s/div i out 2a/div v out 50mv/div 100s/div i out 2a/div v out 50mv/div 100s/div
ISL8205M 11 fn8755.3 august 15, 2016 submit document feedback figure 16. v in = 5v, v out = 2.5v, i out = 0 to 5a, f sw = 2.5mhz, c out = 2x22f ceramic capacitors figure 17. v in = 5v, v out = 3.3v, i out = 0 to 5a, f sw = 3mhz, c out = 2x22f ceramic capacitors start-up t a = +25c, resistor load is used in the test. figure 18. soft-start with 0a load pwm mode, v in = 5v, v out =1.2v, i out = 0a, c out = 2x22f ceramic capacitors, c in = 100f poscap + 2x22f ceramic capacitors figure 19. soft-start with 5a load pwm mode, v in = 5v, v out = 1.2v, i out = 5a, c out = 2x22f ceramic capacitors, c in = 100f poscap + 2x22f ceramic capacitors figure 20. soft-start with 0a load pfm mode, v in = 5v, v out =1.2v, i out = 0a, c out = 2x22f ceramic capacitors, c in = 100f poscap + 2x22f ceramic capacitors figure 21. soft-start with 5a load pfm mode, v in = 5v, v out =1.2v, i out = 5a, c out = 2x22f ceramic capacitors, c in = 100f poscap + 2x22f ceramic capacitors typical performance characteristics (continued) i out 2a/div 100s/div v out 50mv/div i out 2a/div v out 50mv/div 100s/div sw 5v/div v out 500mv/div pgood 5v/div i out 1a/div 500s/div sw 5v/div v out 500mv/div pgood 5v/div i out 2a/div 500s/div sw 5v/div v out 500mv/div pgood 5v/div i out 2a/div 500s/div sw 5v/div v out 500mv/div pgood 5v/div i out 2a/div 500s/div
ISL8205M 12 fn8755.3 august 15, 2016 submit document feedback figure 22. prebias soft-start with 0a load pwm mode, v in =5v, v out = 1.2v, i out = 0a, c out = 2x22f ceramic capacitors, c in = 100f poscap + 2x22f ceramic capacitors figure 23. prebias soft-start with 0a load pfm mode, v in =5v, v out = 1.2v, i out = 0a, c out = 2x22f ceramic capacitors, c in = 100f poscap + 2x22f ceramic capacitors short-circuit protection t a = +25c, v in = 5v, v out = 1.2v, c in = 100f poscap + 22f ceramic capacitors, c out = 2x22f ceramic capacitors, output short-circuit during normal operation. figure 24. output short-circuit pr otection figure 25. output short- circuit protection, hiccup mode figure 26. output short-circuit recover from hiccup typical performance characteristics (continued) sw 5v/div v out 500mv/div pgood 5v/div i out 2a/div 500s/div sw 5v/div v out 500mv/div pgood 5v/div i out 2a/div 500s/div sw 2v/div v out 500mv/div pgood 2v/div i in 2a/div 10s/div sw 2v/div v out 500mv/div pgood 2v/div i in 2a/div 3.2ms/div sw 2v/div v out 500mv/div pgood 2v/div i in 2a/div 3.2ms/div
ISL8205M 13 fn8755.3 august 15, 2016 submit document feedback overvoltage protection t a = +25c, v in = 5v, v out = 1.2v, c in = 100f poscap + 22f ceramic capacitors, c out = 2x22f ceramic capacitors. figure 27. output overvoltage protection power loss t a = +25c, c in = 100f poscap + 22f ceramic capacitors, c out = 2x22f ceramic capacitors. figure 28. power loss at v in = 5v, t a = +25c figure 29. power loss at v in = 3.3v, t a = +25c derating all of the following curves were plotted at t j = +120c. figure 30. derating curves at v in = 5v, v out = 1.2v figure 31. derating curves at v in = 5v, v out = 3.3v typical performance characteristics (continued) sw 2v/div v out 500mv/div pgood 5v/div 500s/div 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 00.511.522.533.544.55 load current (a) vout=1.2v, fsw=1.6mhz pwm vout=3.3v, fsw=3mhz pwm power loss (w) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 load current (a) vout=1.2v, fsw=1.6mhz pwm vout=2.5v, fsw=2.5mhz pwm power loss (w) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 102030405060708090100110120 ambient temperature (c) 200 lfm 0 lfm load current (a) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 102030405060708090100110120 ambient temperature (c) 200 lfm 0 lfm load current (a)
ISL8205M 14 fn8755.3 august 15, 2016 submit document feedback figure 32. derating curves at v in = 3.3v, v out = 1.2v figure 33. derating curves at v in = 3.3v, v out = 2.5v typical performance characteristics (continued) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 102030405060708090100110120 ambient temperature (c) 200 lfm 0 lfm load current (a) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 102030405060708090100110120 ambient temperature (c) 200 lfm 0 lfm load current (a) table 2. ISL8205M design guide matrix (refer to figure 1 ) v in (v) v out (v) f sw (mhz) c in (f) c out (f) r fs (k )r set (k )c ff (pf) 5 0.6 0.8 2x22 1x100 261 open 390 5 0.9 1.2 2x22 3x22 169 200 560 5 1 1.3 2x22 3x22 154 150 560 5 1.2 1.6 2x22 2x22 124 100 820 5 1.5 1.7 2x22 2x22 115 66.5 560 5 1.8 2 2x22 2x22 95.3 49.9 470 5 2.5 2.5 2x22 2x22 75 31.6 330 5 3.3 3 2x22 2x22 59 22.1 330 3.3 0.6 0.8 2x22 1x100 261 open 390 3.3 0.9 1.2 2x22 3x22 169 200 560 3.3 1 1.3 2x22 3x22 154 150 560 3.3 1.2 1.6 2x22 2x22 124 100 820 3.3 1.5 1.7 2x22 2x22 115 66.5 560 3.3 1.8 2 2x22 2x22 95.3 49.9 470 3.3 2.5 2.5 2x22 2x22 75 31.6 330 figure 34. pfm mode operation waveforms clock i l v out nominal +1.2% nominal pfm current limit 0 16 cycles pwm pfm nominal -2.5% pwm load current
ISL8205M 15 fn8755.3 august 15, 2016 submit document feedback functional description the ISL8205M is a single channel 5a step-down high efficiency power module optimized for fpga, dsp and li-ion battery power devices. the module switches at 1.8mhz by default when the fs pin is shorted to vin. the switch ing frequency is also adjustable from 680khz to 3.5mhz through a resistor, r fs , from fs to sgnd. to boost light-load efficiency, ISL8205M can also be configured to operate in pfm mode by pulling the sync pin to sgnd. peak current mode control scheme is implemented for fast transient response. by shorting the comp pin to vin, the module utilizes internal compen sation to stabilize system and optimize transient response. other excellent features include external synchronization, 100% duty cycle operation and very low quiescent current. pwm control scheme pulling the sync pin high (>0.8v) forces the module into pwm mode, regardless of output curr ent. the ISL8205M employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and puls e-by-pulse current limiting. as shown in figure 3 on page 3 , the current loop consists of the oscillator, the pwm comparator, current sensing circuit and the slope compensation for the current loop stability. the slope compensation is 440mv/ts, which changes with frequency. the gain for the current sensing circ uit is typically 140mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier, csa and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the pfet and turn on the n-channel mosfet. the nfet stays on until the end of the pwm cycle. figure 35 shows the typical operating waveforms during the pwm operatio n. the dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier?s (csa) output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during start-up and will be discusse d separately, please refer to ? soft start-up ? on page 16. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. when the comp is tied to vin, the voltage loop is internally compensated with the 55pf and 100k rc network. pfm (skip) mode pulling the sync pin low (<0.4v) forces the module into pfm mode. the ISL8205M enters a pulse-skipping mode at light load to minimize the switching losses by reducing the switching frequency. figure 34 illustrates the skip mode operation. a zero-cross sensing circuit shown in figure 3 on page 3 monitors the nfet current for zero crossing. when 16 consecutive cycles are detected, the module enters the skip mode. during the sixteen detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 3 on page 3 . each pulse cycle is still synchronized by the pwm clock. the pfet is turned on at the clock's rising edge and turned off when the output is higher than 1.2% of the nominal regulation or when its current reaches the peak skip current limit value. then, the inductor current is discharged to 0a and stays at zero (the internal clock is disabled) and the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the pfet will be turned on again at the rising edge of the internal clock as it repeats the previous operations. the module resumes normal pwm mode operation when the output voltage drops 2.5% below the nominal voltage. frequency adjust the switching frequency of ISL8205M is adjustable ranging from 680khz to 3.5mhz via a simple resistor r fs across fs to sgnd. the switching frequency setting is based on equation 1 : when the fs pin is directly tied to vin, the frequency of operation is fixed at 1.8mhz. for selections of switching frequency of typical operation conditions, refer to table 2 on page 14 . more detailed information on recommended switching frequency is provided in ? recommended switching frequency ? on page 17 . overcurrent protection the overcurrent protection is re alized by monitoring the csa output with the ocp comparator, as shown in figure 3 on page 3 . the current sensing circuit has a gain of 140mv/a, from the pfet current to the csa output . when the csa output reaches the threshold, the ocp comparator is tripped and turns off the pfet immediately. the overcurrent function protects the module from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of an overcurrent condition, the upper mosfet will be immediately turned off an d will not be turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. if, figure 35. pwm operation waveforms v eamp v csa duty cycle i l v out r fs k ? ?? 220 10 3 ? f osc khz ?? ------------------------------ 14 C = (eq. 1)
ISL8205M 16 fn8755.3 august 15, 2016 submit document feedback on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the module will be shut down under an overcurrent fault condition. an overcurrent fault condition will result in the module attempting to restart in a hiccup mode within the delay of eight soft-start periods. at the end of the 8 th soft-start wait period, the fault counters are reset and soft-start is attempted agai n. if the overcurrent condition goes away during the delay of 8 soft-start periods, the output will resume back into regulation after the hiccup mode expires. negative current protection similar to overcurrent, the negative current protection is realized by monitoring the current across the low-side nfet, as shown in figure 3 on page 3 . when the valley point of the inductor current reaches -3a for 4 consecutive cy cles, both pfet and nfet are turned off. the 100 in parallel to the nfet will activate discharging the output into regulation. the control will begin to switch when output is within regu lation. the module will be in pfm for 20s before switching to pwm, if necessary. power-good pg is an open-drain output of a window comparator that continuously monitors the module output voltage. pg is actively held low when en is low and during the module soft-start period. after 1ms delay of the soft-sta rt period, pg becomes high impedance as long as the output voltage is within the nominal regulation voltage set by v fb . under output overvoltage fault condition (output voltage is 33% higher than nominal value) or output undervoltage fault condit ion (output voltage is 15% lower than nominal value), the pg will be pulled low. any fault condition forces pg low until the fault condition is cleared by attempts to soft-start. for logic level output voltages, connect an external pull-up resistor between pg and vin. a 100k resistor works well in most applications. uvlo when the input voltage is below the undervoltage lockout (uvlo) threshold, the module is disabled. soft start-up the soft start-up reduces the inrush current during the start-up. the soft-start block outputs a ramp reference to the input of the error amplifier. this voltage ramp limits the inductor current as well as the output voltage speed, so that the output voltage rises in a controlled fashion. when vfb is less than 0.1v at the beginning of the soft-start, the switching frequency is reduced to 200khz, so that the output can start-up smoothly at light load condition. during soft-start, the ic operates in the skip mode to support prebiased output condition. tie ss to sgnd for internal soft-start, which is approximately 1ms. connect a capacitor from ss to sgnd to adjust the soft-start time. this capacitor, along with an internal 1.85a current source sets the soft-start interval of the module, t ss , as shown by equation 2 . c ss must be less than 33nf to insure proper soft-start reset after fault condition. external synchronization control the frequency of operation can be synchronized up to 3.5mhz by an external signal applied to th e sync pin. the rising edge of sync signal triggers the rising ed ge of pwm on pulse. to ensure proper operation, it is recomm ended that the external sync frequency is within 25% of th e switching frequency set by fs pin. enable the enable (en) input allows the user to control the turning on or off of the module for purposes such as power-up sequencing. when the module is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft start-up begins. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the output discharges to pgnd through an internal 100 switch. 100% duty cycle the ISL8205M features a 100% duty cycle operation to minimize switching loss. when the input voltage drops to a level that the ISL8205M can no longer maintain the regulation at the output, the module completely turns on the pfet. thermal shutdown the ISL8205M has built-in thermal protection. when the internal temperature reaches +150c, the modu le is completely shut down. as the temperature drops to +125c, the ISL8205M, resumes operation by stepping through the soft-start. applications information programming the output voltage the output voltage of the module is programmed by an external resistor, as r set in figure 1 on page 1 applied from fb pin to sgnd. r set in combination with the internal 100k 0.5% resistor connected from fb to vsense forms a resistor divider that sets the output voltage. the output voltage is governed by equation 3 . c ss ? f ?? 3.1 t ss s ?? ? = (eq. 2) (eq. 3) v out v ref r set 100k ? + r set --------------------------------------- - ? =
ISL8205M 17 fn8755.3 august 15, 2016 submit document feedback please note that the output voltage accuracy is also dependent on the resistor accuracy of r fs . the user needs to select high accuracy resistors in order to achieve the overall output accuracy. recommended switching frequency with varieties of input and output voltage combinations, one must choose wisely on which frequency to operate at. selection of switching frequency for each v in and v out combination needs to take into account a few trade-offs. generally, lower switching frequency will lead to higher efficiency. however, switching frequency should not be decrea sed too low due to negative current protection limit. moreover, when output voltage is relatively high, low switching frequency will result in more sub- harmonic oscillation. therefore, operating frequency needs to be kept relatively high under high v out conditions. however, again, switching frequency cannot be increased too much. otherwise, the minimum on-time limit could be violated. based on these considerations, figure 36 provides the recommended switching frequency under various typical v in and across v out range. input capacitor selection selection of the input filter capacitor is based on how much ripple the supply can tolerate on the dc input line. the larger the capacitor, the less ripple expected, however, consideration should be given to the higher surge current during power-up. the ISL8205M provides a soft-start fu nction that controls and limits the current surge. the total capa citance of the input capacitor can be calculated based on equation 4 : where: ?c in(min) is the minimum required input capacitance (f) ?i o is the output current (a) ? d is the duty cycle ?v p-p is the allowable peak-to-peak voltage (v) ?f sw is the switching frequency (hz) low equivalent series resistance (esr) ceramic capacitance is recommended to be placed as close as possible to the module input to reduce input voltage ripple and decouple between the vin and pgnd. this capacitance not only reduces voltage ringing created by the switching current across parasitic circuit elements, but also reduces the input noise seen by the module. moreover, the estimated rms ripple current should be considered in choosing ceramic capacitors. the rms ripple current can be calculated by equation 5 each 22f x5r or x7r ceramic capacitor is typically good for 2a to 3a of rms ripple current. refer to the capacitor vendor to check the rms current ratings. based on the above considerations, minimum total input capacitance of 44f is required for ISL8205M. add additional capacitance if possible. use x5r or x7r ceramic capacitors. the placement of the input ceramic capacitors should be as close as possible to the module input. refer to ? pcb layout pattern design ? on page 20 for more information. a bulk input capacitance may also be needed if the input source does not have enough output capacitance. a typical value of bulk input capacitor is 100f. in such conditions, this bulk input capacitance can supply the curren t during output load transient conditions. output capacitor selection ceramic capacitors are typically used as the output capacitors for the ISL8205M. refer to table 2 on page 14 for recommended output capacitor values. bulk output capacitors that have adequately low equivalent series resistance (esr), such as low esr polymer capacitors or a low esr tantalum capacitor, may also be used in combination with the ceramic capacitors, depending on the output voltage ripple and transient requirements. feed-forward capacitor selection in typical applications where the output capacitors are all ceramic, a feed-forward capacitor, as shown as c ff in figure 1 on page 1, is needed to insure loop stability in extreme operating conditions. with internal compensation mode enabled, the c ff values for typical operating conditions are optimized and listed in table 2 on page 14 . please note that, for system parameters that are different from table 2 or external instead of internal compensation is used, the optimized value of c ff needs to be adjusted. table 3. typical voltage setting resistor values v out (v) r set (k ) 0.6 open 0.8 300 1.0 150 1.2 100 1.8 49.9 2.5 31.6 3.3 22.1 figure 36. switching frequency recommendation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 output voltage (v) vin=5v vin=4v vin=3.3v vin=2.6v switching frequency (mhz) c in min ?? i o d1 d C ?? ? v p-p f sw ? ---------------------------------- - = (eq. 4) i in rms ?? io d 1 d C ?? ? -------------------------------- - = (eq. 5)
ISL8205M 18 fn8755.3 august 15, 2016 submit document feedback typical application circuit figure 1 on page 1 only illustrates the application circuit with minimum external components required for operation in pwm mode. a more comprehensive typical application circuit diagram is shown in figure 37 . in this example, a pull-up resistor is added to the pg pin to allow power-good signal monitoring. soft start-up time adjustment is achieved by adding a capacitor, c ss , to the ss pin. typical application circuit of pfm mode operation can also be found in figure 38 . thermal consideration and current derating the ISL8205M?s thermally enhanced package offers typical junction to ambient thermal resistance ? ja of approximately 27.4c/w at natural convection wi th a typical 4-layer pcb board. in applications with elevat ed ambient temperature, the continuous current handling capab ility of the module may need to be derated. the derating curves ( figure 30 through 33 ) are fully tested. they are on the basis of determining the maximum continuous load current while limiting the maximum junction temperature to +120c, which prov ides 5c margin of safety from the rated junction temperature of +125c. the test was done across various typical operating conditions, providing a starting point for system thermal design. note that all the derating curves are obtained based on tests in free air with the module mounted on the ISL8205Meval1z evaluation board with ?direct attach? features. refer to ISL8205Meval1z user guide for evaluation board details. also see tech brief tb379 for general thermal metric information. in real applications where the sy stem parameters and layout are different than the evaluation board, the customer can adjust the margin of safety. other heat so urces and design margins also need to be taken into consideration. figure 37. complete application circuit diagram figure 38. typical application circuit diagram in pfm mode vin en sync pg ss vout fs epad ISL8205M sgnd pgnd sw vsense comp fb 2x22f 2.6v to 5.5v input c in r fs 124k 2x22f c out 1.2v 5a output r set 100k c ff 820pf r pu 10k c ss 15nf pgood vin en pg sync ss vout fs epad ISL8205M sgnd pgnd sw vsense comp fb 2x22f 2.6v to 5.5v input c in r fs 124k 2x22f c out 1.2v 5a output r set 100k c ff 820pf
ISL8205M 19 fn8755.3 august 15, 2016 submit document feedback pcb layout recommendations a few layout considerations need to be taken into account in order to achieve proper operation of ISL8205M. an optimized layout design also allows the module to have lower power loss and good thermal performance. an illustrative layout example is shown in figures 39 and 40 ). key points are listed in the following: ? place the input ceramic capacitors as close as possible to the module input. these ceramic capacitors are used to minimize the high frequency noise by redu cing parasitic inductance of the switching loop. optimized pl acement of these capacitors will not only lead to less switch node ringing, but also minimize the noise seen by the module to insure proper operation. it is recommended to use x5r or x7r ceramic capacitors with a minimum total capacitance of 44f at module input. it is a must that one of the input capacitors (c in1 ), with no less than 3.3f capacitance, should be placed on the same layer (assuming top layer) as the module and within less than 70 mil clearance to module input (refer to figure 39 ). for capacitors on the bottom layer, it is recommended to have one (c in2 ) placed from vin to pgnd copper close to exposed pad (pad 20) vias (as shown in the layout example in figure 40 ). ? use large copper areas for power path (vin, pgnd) to minimize conduction loss and thermal stress. also, it is recommended to use multiple vias to connect the power planes in different layers. use at least 5 vias on the exposed pad 20 connected to pgnd plane(s) for the best thermal relief. ? use a separate sgnd ground co pper area for components that are connected to signal ground. connect sgnd copper to module pad 22 through multiple vias (refer to figure 40 ). because pad 22 is connected to module internal pgnd at single location, the sgnd coppe r area and pgnd plane on the pcb can be left separated. ? it is recommended to keep the sw pads only on the top and inner layers of the pcb. do not expose the sw pads to the outside on the bottom layer of the pcb. in order to minimize switch node resistance, connect pads 21 and 9 using wide trace or shape. ? if remote sense is needed, route remote sensing trace from point-of-load to module vsense pin through quiet inner layer that is shielded by pgnd planes. ? avoid routing noise-sensitive signal traces such as fb, comp near the noisy sw pins. ? the feedback and compensation network should be placed as close as possible to the fb pins and far away from the sw pins. figure 39. layout example - top layer figure 40. layout example - bottom layer
ISL8205M 20 fn8755.3 august 15, 2016 submit document feedback package description the ISL8205M is integrated into a quad flatpack no-lead (qfn) package. this package has such advantages as good thermal and electrical conductivity, low weight and small size. the qfn package is applicable for surfac e mounting technology and is becoming more common in the industry. the ISL8205M is a copper leadframe based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper leadframe and multicomponent assembly are overmolded with polymer mold compound to protect these devices. the package outline, typical pcb layout pattern and typical stencil pattern design are shown in the l22.4.5x7.5 ? package outline drawing ? on page 22 . tb493 shows typical reflow profile parameters. these guidelines are general design rules. users can modify parameters according to specific applications. pcb layout pattern design the bottom of ISL8205M is a leadframe footprint, which is attached to the pcb by surface mounting. the pcb layout pattern is shown in the l22.4.5x7.5 ? package outline drawing ? on page 22 . the pcb layout pattern is essentially 1:1 with the qfn exposed pad and the i/o terminatio n dimensions, except that the pcb lands are slightly longer than the qfn terminations by about 0.2mm (0.4mm maximum). this extension allows for solder filleting around the package periphery and ensures a more complete and inspectable solder joint. the thermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitched thermal vias, which drops down and connects to buried copper planes, should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about 2.0 ounce copper. although adding more vias (by decreasing pitch) improves thermal performance, it also diminishes results as more vias are added. use only as many vias as needed for the thermal land size and as yo ur board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2 mil to 3 mil) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. the stencil aperture size to land size ratio should typically be 1:1. aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the larger thermal lands, an array of smaller apertures inst ead of one large aperture is recommended. the stencil printing area should cover 50% to 80% of the pcb layout pattern. consider the symmetry of the whole stencil pattern when designing the pads. a laser-cut, stainless-steel stencil with electropolished trapezoidal walls is recommended. electropolishing smooths the aperture walls, resulting in reduced surface friction and better paste release, which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a brick-like paste deposit, whic h assists in firm component placement. reflow parameters due to the low mount height of the qfn, ?no clean? type 3 solder paste, per ansi/j-std-005, is re commended. nitr ogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, thus, it is not practical to define a specific soldering profile just for the qfn. the profile given in tb493 is provided as a guideline to customize for varying manufacturing practices and applications.
ISL8205M 21 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8755.3 august 15, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related docu mentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, however, not warranted. please go to the web to make sure that you have the latest revision. date revision change august 15, 2016 fn8755.3 updated note 2 on page 5. updated figure 36 on page 17, corrected typo on legend. may 19, 2016 fn8755.2 related literatu re on page 1: added ug072 link. may 10, 2016 fn8755.1 updated title on page 1 updated default setting from 1.9mhz to 1.8mhz throughout datasheet. replaced figure 1 on page 1. updated figure 3 on page 3. updated typical specification for ?nominal swit ching frequency? on page 7 from 1900 to 1835. added note 8 on page 8. added ?typical application circuit? section on page 18. on page 25, replaced recommended stencil perimeter pads view to match pod. march 21, 2016 fn8755.0 initial release.
ISL8205M 22 fn8755.3 august 15, 2016 submit document feedback package outline drawing l22.4.5x7.5 22 lead quad flat no-lead plastic package rev 0, 9/15 bottom view 1.300 2x 1.610 0.450 2x 0.890 pin 1 identification 11x 0.6 0.710 38x 0.500 bsc 2x 3.110 b ca c c ab 1.125 seating plane side view c 1.90 max 0.05 c c (20x) 0.10 0.05 0.05 0.05 0.08 (2x) (2x) c 0.05 c 0.05 index area pin 1 4.5 b a 7.5 top view 42x 0.220 4x 0.300 2x 0.390 4x 0.390 2x 1.360 21x 0.250 1.000 2x 0.350 1.885 2x 1.230 2.900 1.385 1.250 1.500 1.000 1.000 1.500 located within the zone indicated. the pin #1 identifier may be tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be 5. either a mold or mark feature. 4. dimensions are in millimeters. 1. notes: dimensioning and tolerancing conform to asmey 14.5m-1994. 2. unless otherwise specified, tolerance: decimal 0.05. 3. detail x c 0.203 ref 0 - 0.05 4 see detail x
ISL8205M 23 fn8755.3 august 15, 2016 submit document feedback 3.950 0.00 0.850 1.250 2.7500 3.150 3.950 0.500 0.00 0.00 0.650 1.000 1.250 2.450 2.450 1.135 2.365 1.650 1.700 1.800 0.950 0.365 0.250 1.250 1.125 0.865 0.00 2.450 1.950 1.950 3.450 0.140 0.360 0.640 1.860 0.140 0.360 0.640 1.860 0.140 0.360 0.640 3.360 0.640 1.860 2.140 2.860 3.140 3.360 2.140 2.360 2.640 2.860 3.140 3.360 0.140 0.360 0.640 3.360 0.140 0.140 0.360 1.860 1.650 1.360 1.140 0.860 0.640 0.360 0.140 0.140 0.360 0.640 1.360 pcb land pattern 3.950 2.450 3.950
ISL8205M 24 fn8755.3 august 15, 2016 submit document feedback 1.950 1.659 1.445 1.245 0.741 0.000 0.741 1.245 1.445 1.659 1.950 3.450 3.158 2.100 1.900 0.740 0.240 0.515 0.750 0.835 0.850 1.450 1.810 1.900 2.550 2.100 0.000 1.810 1.950 0.985 1.700 1.226 1.050 0.840 0.600 0.400 0.000 0.050 0.340 0.665 0.689 1.700 1.275 1.310 1.950 0.000 3.460 3.175 2.810 2.340 2.190 0.690 1.160 0.740 2.100 1.900 3.450 3.158 recommended stenci l interior pads
ISL8205M 25 fn8755.3 august 15, 2016 submit document feedback 0.000 0.000 0.000 2.050 1.655 1.845 1.345 1.155 0.845 0.655 0.345 0.155 0.155 1.155 0.345 0.655 0.845 1.845 1.345 1.655 2.050 2.050 2.425 1.975 2.425 1.975 0.000 2.425 1.155 1.675 2.425 2.050 1.820 1.345 1.345 1.155 0.845 0.845 0.655 0.655 0.345 0.345 0.155 0.155 0.975 1.675 3.925 2.655 3.560 3.345 3.155 2.845 2.345 2.155 1.845 1.655 0.845 1.345 1.155 0.155 0.655 0.345 1.845 0.155 0.345 0.655 0.845 1.155 1.345 1.655 2.345 2.655 2.845 2.155 3.155 3.345 3.550 3.925 0.155 0.345 0.655 0.845 1.155 1.345 1.655 1.845 2.155 2.345 2.655 2.845 3.155 3.345 3.550 3.925 0.155 0.345 0.655 0.845 1.155 1.345 1.655 1.845 2.155 2.655 2.345 2.845 3.155 3.175 3.345 3.925 recommended stencil perimeter pads

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